We are looking for a senior design engineer for the Multimedia IP team in Taiwan. The team is involved in IP developments for multiple SOC product lines. In this position, you will have the chance to work on multimedia and interface bridge IPs for our SOC chips.

What you will be doing:

• Front-end design, quality checks for our display subsystem/IP.

• Co-work with verification engineers to ensure that the design is functional.

• Analyze design trade-offs and optimize design based on features, requirements, and system limitations.

What we need to see:

• Masters Degree in EE, CS or CE or equivalent work experience.

• 3+ years of industry experience.

• Proficiency with Verilog and System Verilog.

• IP level design experience.

• Familiar with ASIC design flows.

• Excellent analytical, written, and verbal interpersonal skills and ability to work as part of a team.

Ways to stand out from the crowd:

• Experience in display IP development, display subsystem integration, DP/HDMI, Audio, interconnect, bus bridge.

• Familiarity with SoC concepts such as CPU, memory, interconnects, clock/reset, etc.

• Experience in writing C++/SystemC models.

• Prior experience working in a globally distributed team.

• Proficient scripting experience in Python, Perl, tcl, Make, shell.

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