Job Description

Experience with owning the full chip/Block level and taping out multiple complex

SoCs.Hands-on experience with industry standard Cadence or Synopsys tool suite, and other Sign-off tools from Siemens (Mentor), Ansys etc.

Full-Chip/Block Level Floorplanning, PnR, CTS, different clocking techniques for skew and delay balancing, multiple clock complexity, time budgeting, timing closure techniques, PnR congestion analysis, resolving floorplanning issues, UPF (Low power design techniques), resolving formal verification, layout physical problems, design sign-off tools like and not limited to noise analysis, layout closure, timing and functional eco closure, IR drop analysis etc.

RTL to gds2 flow and basic device physics.

Scripting with tcl, perl, shell etc. to solve the basic design problem.

Internal flow development and understand nuances of Physical Design (Structural Design) flow.

Experience with 7nm technology or below.

Qualifications

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications: The candidate must have a Bachelor's degree in Computer/Electrical Engineering or Computer Science and 10+ years of experience -OR- a Master's Degree in Computer/Electrical Engineering or Computer Science and 8+ years of experience -OR- a PhD in Computer/Electrical Engineering or Computer Science and 5+ years of experience with the following: Experience with owning the full chip level and taping out multiple complex SoCs. Leading the project from all the technical aspects right from RTL2GDS2. Supporting the team members in closing any design issues. Grooming the team members from the technical front. Hands-on experience with industry standard Cadence or Synopsys tool suite, and other Sign-off tools from Siemens(Mentor), Ansys etc. Must have very good understanding of Full-Chip Level Partitioning, Floorplanning, PnR, CTS, different clocking techniques for skew and delay balancing, multiple clock complexity, time budgeting, timing closure techniques, PnR congestion analysis, resolving floorplanning issues, UPF (Low power design techniques), resolving formal verification, layout physical problems, understanding and hand-on experience of digital design sign-off tools like and not limited to noise analysis, layout closure, timing and functional eco closure, IR drop analysis etc. In-depth understanding on rtl to gds2 flow and understanding of basic device physics. Past experience with internal flow development and understand nuances of Physical Design (Structural Design) flow. Minimum 2+ years experience with technically leading junior (fresh out of school) to senior/experienced individual contributors Experience with handling developing PDKs (Process Design Kit) Working experience with cutting edge technology (5nm or below) Very good handle on Tape-out interaction with the foundry and worked on Post-Silicon activities

Preferred Qualifications: Scripting proficiency in PERL, tcl Should be able to own any technical task in SoC physical Design work Documented experience in technically leading past SoC full chip level physical design execution Exposure to various industry standard Physical Design and Sign-Off closure tools Complete Understanding and good understanding of peer domains to Physical Design, viz., RTL, verification, DFx, post-Si etc. Exposure to various industry standard Physical Design and SIgn-Off closure tools

Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.

Inside this Business Group

Intel Foundry is a systems foundry dedicated to transforming the global semiconductor industry by delivering cutting-edge silicon process and packaging technology leadership for the AI era. With a focus on scalability, AI advancement, and shaping the future, we provide an unparalleled blend of an industry-leading technology, a rich IP portfolio, a world-class design ecosystem, and an operationally resilient global manufacturing supply chain. As stewards of Moore's Law, we persistently innovate and foster collaboration within an extensive partner ecosystem to advance technologies and enable our customers to design leadership products. Our strategic investments in geographically diverse manufacturing capacities bolster the resilience of the semiconductor supply chain, particularly for advanced products. Leveraging our technological prowess, expansive manufacturing scale, and a more sustainable supply chain, Intel Foundry empowers the world to deliver essential computing, server, mobile, networking, and automotive systems for the AI era. This position is part of Foundry Services within Intel Foundry. Foundry Services is a customer-oriented service organization. This business unit is completely dedicated to the success of its customers with full P&L responsibilities. This model will ensure that our foundry customers' products will receive our utmost focus in terms of service, technology enablement and capacity commitments.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here. (https://jobs.intel.com/en/benefits)

It has come to our notice that some people have received fake job interview letters ostensibly issued by Intel, inviting them to attend interviews in Intel’s offices for various positions and further requiring them to deposit money to be eligible for the interviews. We wish to bring to your notice that these letters are not issued by Intel or any of its authorized representatives. Hiring at Intel is based purely on merit and Intel does not ask or require candidates to deposit any money. We would urge people interested in working for Intel, to apply directly at https://jobs.intel.com/ and not fall prey to unscrupulous elements.

Working Model

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.